The present invention relates generally to manufacturing and, more particularly, to a method and apparatus for estimating yield fluctuation for back-end planning.
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing the defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
Generally, a set of processing steps is performed on a wafer using a variety of processing tools, including photolithography steppers, etch tools, deposition tools, polishing tools, rapid thermal processing tools, implantation tools, etc. During the fabrication process various events may take place that affect the performance of the devices being fabricated. That is, variations in the fabrication process steps result in device performance variations. Factors, such as feature critical dimensions, doping levels, contact resistance, particle contamination, etc., all may potentially affect the end performance of the device.
After fabrication of the devices is complete, each wafer is subjected to preliminary functional tests. Wafers that pass these tests are then cut to singulate the individual die, which are then packed in substrates. Packed dies are then subjected to additional tests against the specification of customers' orders to determine performance characteristics such as maximum operating speed, power, caches, etc.
Exemplary tests include initial class tests (ICL) that is a preliminary test for power and speed. ICL testing is usually followed by burn-in (BI) and post burn-in (PBI) tests that test packaged die under specified temperature and/or voltage stress, and automatic test equipment (ATE) tests that test die functionality. Then, packaged dies with different characteristics go through system-level tests (SLT) in which they are tested against customer requirements on specific electrical characteristics. In SLT, packaged dies are tested in an actual motherboard by running system-level tests (e.g., variance test programs). After completion of the testing, the devices are fused, marked, and packed to fill customer orders. This back-end processing is commonly referred to as the test, mark, pack (TMP) process.
Based on the results of the performance tests each device is assigned a grade, which effectively determines its market value. In general, the higher a device is graded, the more valuable the device. However, some applications do not require high-end devices. Accordingly, maximizing the profitability of the fabrication facility does not necessarily equate to maximizing the output of high-grade devices.
Because of the variation in performance of the end product devices, it is difficult to predict the throughput of the TMP line for devices meeting the requirement for a particular order part number (OPN). An OPN is associated with various parameters, such as speed and test requirements, that die must meet, which can be highly different for dies on the same wafer due to variance in process control during wafer fabrication. Hence, the supply of completed devices may not always result in desired number of outputs for a qualified OPN. For example, if a large number of high performing devices (i.e., more expensive devices) have been produced, but the current demand is for lower cost devices (i.e., slower), orders may not be able to be filled with the desired grade device. As a result, the manufacturer may be forced to sell devices of a higher grade at a lower price to fill the order. If the demand is for higher grade devices, and the supply of higher grade devices is diminished, the manufacturer may be unable to fill the order at all. Either situation results in lost profits for the manufacturer.
New product revisions typically have low yields and high yield variances over the test, mark, and pack (TMP) process. This fluctuation may result from design defects or narrow yield control limits. Also, new test process flows or new test programs typically result in increases in yield fluctuations. The testing process assigns devices to bins in accordance with their performance characteristics. Because TMP is the last process before finished packages are shipped to customers, the ability to accurately estimate the yield fluctuation during production planning and control is an important aspect of ensuring that commitments to customers may be met. Typically, fabrication personnel manually estimate the number of devices to dispatch into the TMP process to achieve output levels of a particular OPN sufficient to fill customer orders. This manual process relies heavily on planner experience and preferences. For example, different planners may add different buffers of additional devices to attempt to compensate for yield fluctuation. However, as the yield and yield fluctuation vary over time, such as with the product lifecycle, this approach may not reliably ensure that enough devices are available. Inconsistencies in yield prediction and buffering techniques impacts production inventories and production waste, reducing the overall efficiency of the production line. When more devices are completed than are needed to fill customer orders, the extra devices are stored in inventory for future demands, which results in week-to-week inventory costs. Overproduction also negatively impacts equipment capacity as equipment resources are consumed unnecessarily. If customer demand is not met, the unfinished portion rolls over to the following week, which increases production pressure for the following week and reduces customer satisfaction.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the present invention described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the present invention. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.